AMD’s Helios claims 30% per-dollar lead over Nvidia’s Vera Rubin

AMD is rolling out Helios, its first true rack-scale AI platform, and it is making a bold bet against Nvidia’s Vera Rubin: Helios’ higher peak performance is estimated to deliver a 30% performance per dollar lead over the competition. The headline number is rooted in a spec sheet that, in AMD’s telling, makes Helios bigger and faster than Nvidia’s existing Blackwell-based rack systems and also Vera Rubin, including the rack itself.

Helios is built as a 72-GPU system arranged across 18 liquid-cooled compute blades. Each blade carries four Instinct MI455X accelerators, powered by a single 96-core Venice Epyc CPU up to 5 GHz (with the possibility for OEMs and hyperscalers to spec up to 256 cores per blade). Physically, Helios uses the OCP Open Rack Wide form factor at 1.2 meters wide and 44U high, which AMD notes is nearly twice the size of Nvidia’s NVL72. The extra space matters because it supports more aggressive internal plumbing and power delivery: under load Helios is built around a 50 volt liquid-cooled DC bus bar that can deliver between 225 and 245 kW.

On paper, AMD says the architecture turns that real estate into measurable advantages. Compared to Vera Rubin, Helios boasts 50% more HBM4 and improvements in scale-out bandwidth, along with 15% to 25% higher performance for AI training. There is also a nuance AMD is leaning on: Vera Rubin’s adaptive compression tech is supposed to give it a 25% lead over Helios at FP4, but that advantage is framed as an inference-focused benefit. For workloads that cannot use that advantage, Helios offers 15% higher peak FP4 FLOPS. In other words, this is a two-front fight: where compression helps Nvidia, Helios tries to make up for it with raw bandwidth and peak math, and then it leans on claimed performance-per-dollar superiority.

That performance case is tied to the Instinct MI455X, AMD’s new GPU built on its 5th-gen CDNA compute architecture. The chip is described as a silicon sandwich that stitches together I/O, compute, and memory in a single package. MI455X includes 24 chiplets using a mix of 2.5D and 3D packaging. It has eight compute dies fabricated on TSMC’s 2nm process, stacked atop a pair of 3nm fabric and cache dies (FCDs). The FCDs are positioned as cache-heavy interposers with 96 MB of L2 cache each, and they also host the memory controllers for the chip’s 12, 36 GB HBM4 stacks.

The MI455X introduces another architectural shift: AMD moves I/O responsibilities out of the traditional under-compute approach. Instead of placing the I/O die underneath the compute like prior Instinct designs, MI455X uses two new dies (also on TSMC 3nm) responsible for chip-to-chip communication. AMD says this allows the chip to behave as one large GPU or two smaller ones depending on the selected NUMA configuration, and it supports spatial partitioning into up to eight virtual GPUs.

Under the hood, the CDNA improvements are aimed at AI-centric workloads. Compared to last year’s MI355X, AMD claims as much as 4x higher floating point performance for AI workloads. MI455X forgoes FP64 entirely to dedicate die area to AI-focused datatypes like MXFP4 and MXFP8, and it adds support for 16 and 32 block scale data types. For anyone needing FP64 compute, AMD points to a different, HPC-focused SKU. AMD also changes the memory system approach, opting for a larger shared L2 cache and removing its last level “Infinity” cache. AMD fellow Alan Smith is cited saying the bandwidth delivered for one L2 cache on MI455X is 1.5x the aggregate bandwidth of the Infinity cache on MI355X. Add in execution engine changes to boost IPC and a new DMA engine designed to minimize data movement, and the goal becomes clear: keep the GPU fed, reduce unnecessary transfer costs, and spend silicon where AI math happens.

Now to the rack, because the interconnect is where these systems win or collapse. Helios and Nvidia’s NVL72 are both described as remarkably similar at the highest level: each packs 72 GPUs over 18 liquid-cooled compute blades. But the interconnect philosophy differs. Nvidia uses NVLink, while AMD is tunneling Ultra Accelerator Link over Ethernet (UALoE). That means AMD does not need bespoke switches, and system builders can use merchant silicon like Broadcom. Helios reference design uses 12 Broadcom Tomahawk 6 switch ASICs at 102.4 Tbps spread across six switch trays. Each provides 512 lanes of 200 Gbps connectivity, enough to feed each MI455X with 3.6 TB/s of bidirectional bandwidth.

Helios also pushes scale-out networking harder. Nvidia’s Vera Rubin pairs each GPU with a single 1.6 Tbps ConnectX-9 superNIC, while AMD assigns each MI455X three 800 Gbps Pensando Vulcano network cards for 2.4 Tbps of scale-out bandwidth per accelerator. For front-end communications like management, API traffic, and storage, each of Helios’ 18 compute blades includes a 400 Gbps Pensando Salina data processing unit (DPU). If AMD’s performance claims hold and power estimates are in the right ballpark, the platform could be both faster than Vera Rubin and more power efficient, though the source notes that Nvidia has not shared system-level power consumption for Vera Rubin yet. The reporting frames “best estimates” for peak power consumption at around 240 to 250 kW for Nvidia’s system.

All of this raises the question executives should actually worry about: will the marketed peak FLOPS show up when software hits the real world? The Register points out a familiar problem. Peak FLOPS are a mathematical approximation based on OPS per clock cycle, but modern accelerators run boost curves tied to power and thermals, and AI workloads are dominated by matrix multiplication where the matrix shape and software kernels determine how close the hardware can get to peak. FLOPS on spec sheets act like ceilings that are functionally impossible to reach. AMD knows this, and the source says the company has started tweaking marketing toward measured performance instead of only theoretical numbers. With the newly unveiled MI355X, AMD listed both peak and achieved FLOPS, and with Helios it follows a similar path.

Ahead of Thursday’s keynote, Anush Elangovan, VP of AI software at AMD, is quoted saying that in real-world testing MI455X achieved 20 petaFLOPS of FP4 performance, which is half of peak. The more meaningful question becomes who gets closer to the roofline, not who has the higher theoretical ceiling. Elangovan also remains confident that MI455X delivers higher performance than any accelerator on the market, with the source quoting that it is “delivered bandwidth and flops,” and that “There is no other accelerator that I have”... but the quote is cut off in the provided material.

Strategically, Helios matters because it is arriving at the same time Nvidia’s Vera Rubin is on the table, making this less of a slow technology cadence and more of a direct competitive handshake. For datacenter buyers, hyperscalers, and the investors funding the next wave of AI infrastructure, the decision is not “whose chip is faster in a vacuum.” It is whether the rack-level design, memory capacity, scale-out fabric, and measured AI training or inference behavior justify power and procurement tradeoffs. If AMD’s Helios actually delivers on the 30% performance per dollar promise with competitive power efficiency, it forces the market to reprice the cost of compute at the rack level. If it does not, the spec-sheet fight becomes a branding fight, and the industry keeps following Nvidia’s lead. Either way, Helios turns the spotlight to something boards and CFOs should track closely: achievable performance per watt and per dollar, not just peak throughput.