IBM’s Jay Gambetta says “sub-1 nanometer” nanostack boosts AI data center chips

IBM’s Jay Gambetta, director of IBM Research and an IBM Fellow, is making a bold claim about the next AI compute wave: a “world’s first sub-1 nanometer chip technology” built around what IBM calls a “nanostack” transistor architecture.

The headline detail is not marketing fluff. IBM says its nanostack design can integrate nearly 100 billion transistors on a chip sized “the size of a human fingernail,” roughly twice the transistor density of its previous generation. And IBM’s promise tied to that packing density is equally direct: compute performance and energy efficiency improvements for AI data centers, including a future where computing gets significantly more powerful without a corresponding increase in energy.

So what does “sub-1 nanometer” actually mean here? It is worth spelling out because in conventional silicon scaling, you would expect sub-1nm to be a literal promise about physical dimensions. IBM’s own framing acknowledges the problem: it is impractical to build reliably functional chips with transistors and other features smaller than 1 nanometer due to physical limitations. In other words, if you interpret “sub-1 nanometer” as a literal manufacturing breakthrough that makes features smaller than 1nm, the claim runs into physics and fabrication realities.

IBM’s counter is architectural. It is basically claiming that its nanostack architecture can deliver the computing performance improvements you would expect from a theoretical chip where the physical features were smaller than 1nm. That is a clever, important distinction for executives. In boardrooms, teams do not just ask whether something sounds advanced. They ask whether it reduces risk by working around hard-to-manufacture constraints, and whether it changes the economics of compute in a world where AI demand is pushing energy use, cooling capacity, and data center power availability into the spotlight.

Energy efficiency is not a side quest for AI data centers anymore. Training and inference at scale are power-sensitive, and chips are the lever operators pull when they need more throughput without exploding power consumption. IBM’s language is explicit that the nanostack approach is intended to point toward a future where computing power rises without a matching energy increase. If IBM can truly translate transistor-density gains into real-world performance per watt, that is not just a technical milestone. It can influence procurement cycles, total cost of ownership, and the competitive positioning of chip vendors competing to be the default silicon inside AI infrastructure.

The transistor-density number is also a signal about where IBM believes the industry momentum is. “Nearly 100 billion transistors” on a chip roughly the size of a human fingernail, at about twice the density of the previous generation, implies IBM is pushing for incremental gains that compound into meaningful performance and efficiency shifts. The difference between “we improved something” and “we doubled density” is what grabs attention. Higher density can enable more parallel compute or more sophisticated on-chip structures, but it also increases design complexity and heat management concerns. IBM is essentially arguing it can get the upside without paying the full downside that often comes with aggressive scaling.

There is another strategic angle here: this is a claim about an architecture for AI data centers, not a general-purpose consumer chip. AI data centers care about predictable performance, power envelopes, and how reliably chips can be fabricated and deployed. That focus matters because “sub-1 nanometer” as a phrase could invite skepticism. The source provides the skepticism-prevention line: physical limitations make sub-1nm features hard, so IBM frames nanostack as a way to approximate the benefits. For decision-makers, that framing can be the difference between “sounds impressive” and “is plausibly deployable.”

For investors and operators watching semiconductor roadmaps, IBM’s positioning is a reminder that the next step in computing may not always be a simple continuation of shrinking transistors to smaller and smaller physical sizes. It can also be architecture-first, where clever stacking, layout, and integration techniques produce the functional equivalent of smaller features. That matters because manufacturing constraints, yields, and cost curves are the real bottlenecks behind many scaling fantasies.

In the end, the real stake is the one IBM highlights: getting more powerful computing without a matching energy increase. If IBM’s nanostack approach holds up, it can strengthen IBM’s credibility in the AI infrastructure arms race by offering a path to better performance and efficiency that avoids the most brutal limits of going below 1nm. And if it does not, the industry still learns something valuable: that “sub-1 nanometer” claims will be judged less by the slogan and more by whether architecture can deliver the expected gains under real physical constraints.