Qualcomm’s Tony Pialis bets on stacking DRAM over compute to sell AI250 inference

Qualcomm’s datacenter push just got a very specific, very physical update: Tony Pialis, Qualcomm’s EVP of datacenter, wants to “bury the compute under the DRAM.” The move is being packaged as high-bandwidth compute (HBC), where Qualcomm stacks layer upon layer of DRAM on top of its XPUs to form a single unified compute and memory module.

The headline claim, announced during Qualcomm’s 2026 investor day last week, is designed to sound like a punchline and land like a weapon. Qualcomm says the AI250 will deliver 768 GB of memory capacity and up to 133 TB/s of effective memory bandwidth per card. It also frames this as better inference economics than today’s GPUs, by shortening and accelerating the path between logic and memory. That is the promise. The follow-up question is whether the industry can trust “effective” bandwidth the way it trusts real, measurable bandwidth.

To understand why Qualcomm is betting the farm on this, you have to zoom out to the AI accelerator race. Qualcomm is not new to AI chips. Essentially every Snapdragon processor sold today includes an NPU. But datacenters are a different battlefield. Qualcomm’s AI accelerators have not captured the same excitement as Nvidia, AMD, or even startups like Cerebras. That matters because in the datacenter, the best hardware story often wins distribution, and distribution is everything when your customers are building at scale. Qualcomm’s strategy is trying to jump past the “compute only” conversation and go straight for the bottleneck that actually limits many workloads: moving data.

Qualcomm’s HBC is a near-memory compute architecture. The company claims it can offer “all of the performance advantages of SRAM,” but with the density and memory capacity of HBM (high-bandwidth memory) stacks. The stack, at a high level: compute and DRAM are combined in a 3D-stacked silicon design using through-silicon vias (TSVs). Pialis used a road analogy to explain the benefit: if you do work in the same building you live in, you spend less time and energy traveling. In chip terms, Qualcomm argues that shortening the compute-to-memory path reduces power draw, cuts heat, and removes the need for the expensive “road of silicon interposer” that HBM solutions rely on.

Now, the part that makes engineers squint and executives ask for receipts: Qualcomm’s emphasis on “effective bandwidth.” For the AI200-based Dragonfly systems rolling out this year, Qualcomm claimed 414 TB/s of effective memory bandwidth across all 56 chips. On paper, that sounds more realistic than the AI250 figure, but it also raises red flags when you try to reconcile it with the underlying LPDDR5x speeds. Qualcomm says the result is tied to pure physical bandwidth of the LPDDR interface, but it declined to provide specifics on how it achieves what it took Nvidia eight HBM3e stacks to do. The key is that Qualcomm is not merely measuring bandwidth in the conventional sense. It is using “effective” multipliers as a feature of how HBC changes where compute happens, and how much data must be shuttled.

That architecture matters most for decode. Qualcomm’s disclosures emphasize that higher memory bandwidth primarily benefits decode, when models generate tokens one after another and must stream active weights from memory for each step. Decode is not particularly compute intensive. So moving some of the XPU’s compute under the DRAM can make sense because it also helps avoid thermal constraints that come with stacking lots of compute under multiple layers of DRAM. Qualcomm says the AI250 can be used as a standalone inference accelerator, but it is also optimized to fit into disaggregated inference setups where GPUs (or other Qualcomm parts) handle prompt processing while the AI250 accelerates memory-intensive decode.

There’s an important caveat that sits right between the ambition and the boardroom skepticism. Peak FLOPS are notably missing from the AI250 disclosures. Qualcomm declined to share specifics upon request, so the argument is currently economic and architectural, not “raw compute dominance.” And HBC is also not entirely a category invention. Qualcomm is early in pushing near-memory compute hard, but it is not alone. Nvidia and AMD are rumored to be working with HBM suppliers and TSMC to develop custom base dies to boost next-gen chips, though it’s unclear how much compute is integrated. Startup d-Matrix is also developing accelerators using 3D stacked DRAM to extend in-memory compute.

Qualcomm’s own framing tries to draw a line between HBC and HBM. It says HBC uses LPDDR memory in a purpose-built near-memory computing architecture that combines compute and highly-accelerated memory bandwidth within a 3D-stacked silicon design. It claims HBC is distinct from HBM because HBM uses more DRAM stacks, routing via a 2.5D interposer, and does not do computing in the base logic die. In other words: even if the stacking concept overlaps, Qualcomm argues the compute placement and efficiency target are the differentiator.

But for executives, the most immediate second-order bet may be software, not the stack. Qualcomm’s investor day also coincided with its acquisition of AI software startup Modular. Modular was founded by Tim Davis and Chris Lattner, the latter known for LLVM, Clang, the Swift programming language, and MLIR. Modular built Mojo, a low-level programming interface for GPUs designed as a higher-performance alternative to Nvidia’s CUDA or AMD’s HIP and ROCm. Qualcomm’s pitch: customers should be able to write performant AI apps that run regardless of the underlying hardware, reducing platform lock-in. That could matter in a disaggregated world where heterogenous deployments are the norm, such as using GPUs for prefill and AI250s for decode in whatever ratio fits the application.

So what does this mean for competitors and decision-makers? Qualcomm is trying to win by redefining the bottleneck, then backing it with a software layer meant to loosen CUDA’s grip. Whether HBC delivers on the “effective bandwidth” story will determine if AI250 becomes a credible alternative at the rack level. And if Qualcomm can translate HBC’s inference economics into adoption, Nvidia, AMD, and their partners will have to work harder not just on FLOPS, but on the data movement economics that increasingly decide total cost and throughput.